The changing gain issue certainly squares with some of the problems that I see in the time domain simulation. The stability problem is at its worst at the peak of the AC cycle.
I re-ran the time domain simulation last night and came to some interesting empirical conclusions, regarding stability:
1) The rail voltage needs to be 1.5 times the maximum peak AC output voltage. This keeps you away from running the inverter near 100% duty cycle, where many of the chaotic stability problems are encountered.
2) The zero in the current mode crossover needs to be set at 1/10 the switching frequency. Although the theoretical maximum is Fsw / 2PI, chaotic instability appears when the current loop is run this fast. I made this determination by eliminating the voltage feedback loop, and initially running the amplifier as a voltage controlled current source.
3) With the current loop crossover zero set at 1/10 the switching frequency, a very stable current loop results, provided that a final roll-off pole is not introduced at or below the switching frequency. Otherwise, chaotic instability begins to appear. As mentioned originally, I'm limiting the inductor AC signal in the error amplifier output to 1/2 the peak-to-peak triangle wave amplitude.
4) Unfortunately, even with a stable current loop, when you close the voltage loop, there are more problems to contend with. The unity gain crossover point on the voltage loop has to be set at 1/10 the crossover point of the current loop. So if I'm switching at 120 KHz, and the current loop is crossing over with a zero at 12 KHz, then the voltage loop unity gain crossover point is set at 1.2 KHz.
Yes, I get a clean 400 Hz sine wave with this compensation: But I've just thrown away all the purported wideband advantages of average current mode control.
A couple of more details: This study is part of a retrofit design for a three phase 400 Hz inverter. The inverter was originally run with voltage mode feedback and a 40 KHz switching frequency. Each power stage is a half bridge rather than a full bridge. Harmonic suppression traps in the retrofit design are installed after the initial LC output filter and set at 120 KHz and 240 KHz, to suppress the switching frequency and the 2nd harmonic. The SPICE simulation is being run on just one phase for now.
After I've done a little more work to check out some residual issues, I'm thinking about putting together a short paper with the results of the SPICE simulation study and posting it on-line. The resulting waveforms are interesting to look at.
The chaotic instability problems I've run into are traditionally indicative of a hidden, right half plane zero. However, there may well be another mechanism involved, including sub-harmonic oscillation, related to the PWM modulation scheme and the inductor current.
This is the stuff that IEEE theoretical papers and PhD thesis are spawned from. I'm just an engineer getting paid to do a feasibility study for an inverter upgrade. Obviously, average current mode control will not be considered a design option at this point. I need a proven design approach with a solid theoretical foundation, one that will pass muster with a design review committee.